Georgia Institute of Technology
School of Electrical and Computer Engineering
Cadence University Program Member
Cadence Tools in the ECE Curriculum
- ECE 3042 and ECE 3043 use version 16.5 of Cadence/Orcadlite/PSpice for basic instruction in SPICE
- ECE 3060 (VLSI and Advanced Digital Design): The Virtuoso schematic/layout editors along with Diva DRC/LVS tools are used by the students to design a 16bit Microprocessor. The students uses the Cadence tools to design the schematic and the layout of individual units such as Adder, Register File, Decoders, etc. and perform DRC/LVS checks on them. The Cadence tools in this course introduces students to the basic VLSI design skills.
- ECE 6130/4130 (Advanced VLSI Systems): The Virtuoso schematic/layout editors and Diva/Calibre DRC/LVS/Extraction tools are used in this course to teach students advances concepts of digital system design using the NCSU Design Kit. The course uses Cadence Virtuoso as the only acceptable tool for a semester long design project in this course. For example, in last two years in the design project students are designing a three stage pipelined system - an SRAM array, a one-cycle Interconnect, and a fast adder - using Cadence tools in this course. The design is performed at advanced technology nodes (e.g. IBM130nm, FreePDK45nm etc.) with aggressive voltage/frequency targets (~1GHZ at 0.8-1V supply). A significant number of students in this class also uses Spectre simulation environment for design while a fraction of students uses HSPICE for simulations.
- ECE 6133 (Physical Design Automation VLSI Systems): Encounter and Virtuoso for digital IC designs.
- ECE 6414 (Analog Intergrated System Design): Custom IC and Verification are utlized for projects involving deep brain stimulation, wireless cardiac monitoring and electrocardiogram monitoring.
- Cadence is used for design projects in the graduate course “Wireless IC Design” (ECE6420). Standard device models are used in conjunction with Spectre and SpectreRF simulation in Cadence to design circuits for Ultra Wide-Band (UWB) applications. Baseband and time-domain simulations of analog front-ends and back-end circuits are performed.
- ECE6430 (MOS Digital ICs): The MOS Digital IC course uses Virtuoso schematic/layout editor along with Spectre to teach students advanced concepts of digital circuit design. In this course, Cadence tools are normally used to solve small scale design problems in Homeworks.
- ECE8893 (Digital System in Nanometer Nodes): In this course, each student defines his/her own design project ranging from digital system integration to low-level circuit techniques. All the projects (~12-15) are implemented using Cadence design tools including Virtuoso, Diva or Calibre DRC/LVS/Extraction and SoC encounter (for Auto Place/Route). The designed projects may lead to Fabrication of test chips.
Cadence Tools in ECE Research ProjectsCadence software is being used in many research projects in the School of Electrical and Computer Engineering. They include the following, wide-ranging initiatives.
- The Microsystems Packaging Research Center is designing and building prototypes, which demonstrate next generation packaging technology developed at the center.
- Integrated systems for segmented locomotion are being built in the Neuromorphic Systems Laboratory, with funding from the National Science Foundation.
- The Cooperative Analog and Digital Signal Processing (CADSP) laboratory has used the Cadence tools for an intelligent audio processing project funded by National Semiconductor. Their goal is to create a low-power analog front-end that triggers a more complicated Digital Signal Processing system. They used Cadence to simulate the individual components (filters, zero-crossings detector, and classification circuit) and the complete system. This work required them to use audio files as stimuli to analog circuits in Cadence. As a result, they created a MATLAB function, wav2cadence, that converts a sound file into a SPICE piece-wise-linear-source (PWLS) that can be included in a Cadence spectreS simulation, (simply by including the file under the "Environments" tab and rebuilding the netlist). They also used the ocean feature to communicate with MATLAB such that they could automatically adjust simulation parameters with a MATLAB script.
- The Integrated Sensors & Systems Lab (i-SensSys) led by Prof. Oliver Brand utilizes Cadence applications for the design and development of intergrated microsensors and their front-end signal conditioning circuitry.
- The Georgia Tech Analog, Power, & Energy ICs Lab uses the Cadence tools for the simulation, layout, and verification of integrated circuits (ICs) designed, developed, built, and evaluated for the purpose of furthering their research in the field of analog, power, and energy ICs. The files generated from the Cadence environment are used to submit IC prototypes to foundries like those supported by MOSIS.
- Dr. Cressler uses Cadence in his research team as the standard platform for IC design in SiGe technology. The tools used include icfb/msfb, layout, layout XL, schematic, hierarchy editor, diva, Assura + Assura RCX, Calibre, Spectre, Sonnet plug in, ADS Dynamic Link / rfde, GoldenGate, Encounter, Synopsis, AMS, ncverilog, and SimVision.
- The Georgia Electronic Design Center (GEDC) supports world-class research that fosters the development and design of new communications technology in wireless/RF, wired/copper and fiber channel applications.
- The Georgia Tech Computer Aided Design (GTCAD) Lab lead by Dr. Sung Kyu Lim have taped out a 3D IC design using SOC Encounter, QRC Extraction and Virtuoso Cadence design tools and others. The tool sets used are Custom IC and Digital IC.
- The Gigascale Reliable Energy Efficient Nanosystem (GREEN) Lab led by Prof. Saibal Mukhopadhyay uses Cadence tools for virtually all of their research efforts on Digital Circuits/Systems ranging from memory design, signal processing circuits/systems, power/thermal management for multi-core design, 3D ICs design, and biomedical circuit/system design. GREEN Lab is currently using Cadence tools to tape-out a test chip in FD/SOI technology offered through MIT-Lincon Lab, GREEN lab envisions using Cadence tools (Virtuoso, Spectre, SoC Encounter, etc.) to tape out atleast one test chip every year.
- The GT-Bionics Lab utilizes Custom IC, Verification and Allegro for projects related to neural interfacing and implantable biomedical devices.
- The Microprocessor Architecture ReSearch (MARS) Lab led by Prof. Hsien-Hsin S. Lee uses Cadence tools including SoC Encounter and Virtuoso to design and tape out their 3D-IC multicore processor and accelerator.
- The Yield Enhancement and Testing Research Group (YETRG) led by Prof. Linda Milor utilizes Allegro, SOC Encounter, QRC Extraction, RTL Compiler, Virtuoso, IUS for Custom IC and Digital IC.
Value Added Items
- The Electronic Design Automation Wiki assists students and research groups with learning how to use available EDA tools.
- A technology library for MOSIS 0.5 micron technology was created. A brief description of the library is here.
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Last revised on April 11, 2014.